In many asynchronous circuits it is desirable that the delay characteristics of one circuit closely track or vary in a certain relationship to that of another. For most devices, the delay characteristics change over temperature, process and supply voltage variations. In medium scale integration (MSI) , the two circuits are designed using separate integrated circuit (IC) devices. In this technology it is necessary that a designer account for these variations in the delay of the individual IC devices.
Although the two circuits are designed on a single IC in very large scale integration (VSLI), the delay characteristics of the two circuits may not necessarily track. For application specific integrated circuits (ASIC), the problem of tracking is further compounded when the device is compilable because performance of the circuit may depend on the aggregate size of the compiled device. In compilable ASICs, the user of the IC defines the memory requirements of the IC. In particular, the memory size, e.g., the number of rows and columns of memory cells as discussed below, are defined. In many ASIC designs, the elements of the memory, such as memory cells, sense amplifiers (amps), or decoders, all of which are discussed below, are prearranged as "tiles" within the IC. After the user defines the requirements of the IC, the interconnections between the "tiles" are compiled by software that determines the interconnections and routes them. Because standard drive circuitry "tiles", e.g., precharge pulse generators, have predetermined timing characteristics, the timing of the "tile" varies as the memory size varies, because the load on the "tile" varies. Thus, a precharge pulse generator " tile" designed to provide a pulse at a given time generates a pulse at different times for different memories.
Traditionally, two circuits are designed to track each other by designing the circuits for worst case timing, thereby sacrificing performance under other conditions. However, the increasing demands on system throughput require improved performance. Worst case timing designs do not satisfy the new performance demands.
FIG. 9A is a schematic of a prior art pulse generator or chopper circuit. The chopper circuit is designed to produce a pulse that ends at a time coincident with the edge of a pulse in an output of a second circuit. FIG. 9B is the timing waveforms of the pulse generator. A chopper circuit 10 has a two-input NAND GATE 12 that is enabled by a clock 14 on a first input. The second input of the NAND GATE is the delayed clock or output 22 of a chain of an odd number of inverters 16. As will be discussed below, any odd number of inverters may be chosen so that the desired output 18 has a pulse width 20 that is determined by the delay time through the chain of inverters. For simplicity, three serially connected inverters 16-1, 16-2, and 16-3 are shown with the clock 14 inputted into the inverter 16-1. The delayed clock 22, the output of the inverter 16-3, is inputted into the second input of the NAND GATE 12. Because the number of inverters is odd, the output of the inverter 16-3 has an opposite value of the clock 14 except for the time after the clock 14 switches values and before the transition propagates through the inverter chain 16.
Referring to FIG. 9B, the output 18 from the NAND GATE 12 is a logic 1 except when both inputs, the clock 14 and the delayed clock 22, are high or a logic 1. When the clock 14 makes a transition from a logic 0 to a logic 1 at time 24, both the clock 14 and the delayed clock 22 are a logic 1. This state changes the output 18 of the NAND GATE 12 to a logic 0. The transition of the clock 14 also propagates through the inverter chain 16; after a time equal to the pulse width 20, the delayed clock 22 becomes a logic 0. At this time, the clock 14 and the delayed clock 22 are a logic 1 and a logic 0, respectively. The output 18 of the NAND GATE 12 correspondingly goes to a logic 1. Thus, the transition of the clock 14 from a logic 0 to a logic 1 causes a pulse with a pulse width 20 on the output 18.
The ability of the pulse generator described above to track a second circuit raises several problems. First, the pulse width is dependent on the load on the output of the circuit, process variations in the manufacture of the gates, and other characteristics of the NAND GATE. Second, the temperature, process and voltage characteristics of the inverter or feed-back chain may prevent tracking of the delay characteristics of the second circuit. Finally, the delay of the delay circuit chain is fixed and has no provision for adjustment as the delay of the second circuit changes, although in compilable cells, the delay of the second circuit frequently changes.
FIGS. 10A and 10B are schematics of prior art open loop and closed loop chopper circuits, respectively. The open loop chopper circuit 26 shown in FIG. 10A functions in a manner similar to the prior art circuit 10 shown in FIG. 9A. A chain of delay circuits 28-1 through 28-N replaces the inverter chain 16. Any number, N, of delay circuits 28 may be used provided that the output of the delay circuit 28-N has an opposite logic value of the clock 14 after a transition in state of the clock 14 has propagated through the delay circuit chain 28. The output 18 of the NAND GATE 30 is a pulse having a pulse width equal to the delay time of the delay circuit chain 28. The delay of NAND GATE 30 can be disregarded if the delay time through the NAND GATE 30 is very small compared to the delay through the delay chain 28. Because this circuit operates similar to the chopper circuit in FIG. 9A as described above, it has similar disadvantages.
In designs where the delay through the NAND GATE 30 is not small, the closed loop chopper circuit 32 of FIG. 10B is used. In this circuit, the output 34 of the NAND GATE 36 is an input to the delay circuit chain 38 whose output is an input to the NAND GATE 36. The clock 14 is an input to the second input of the NAND GATE 36. The delay circuit chain 38 has N delay circuits 38-1 through 38-N and functions in a manner similar to the delay circuit chain 28 of chopper circuit 26. Any number, N, of delay circuits 38 may be used provided that the output of the delay circuit 38-N has the same logic value as the output 34 after a transition in state of the output has propagated through the delay circuit chain 38. The closed loop chopper circuit 32 functions in a manner similar to that of the open loop chopper circuit 26 except that, when the clock 14 makes a transition from a logic 0 to a logic 1, the output 34 is a sequence of pulses each having a pulse width equal to the delay through the delay circuit chain 38 plus that of the NAND GATE 36. This toggling between logic states will continue until the NAND GATE 36 is disabled by switching the clock 14 to a logic 0. This continuous oscillation is easily visualized. Initially clock 14 is a logic 0, the output 40 of the delay circuit 38-n is a logic 1 and output 34 is a logic 1. After the clock 14 is switched from a logic 0 to a logic 1, the NAND GATE 36 is enabled and the output 34 goes low to a logic 0. The new value of the output 34 propagates through the delay circuit chain 38 causing its output 40 to become a logic 0. The NAND GATE 36 inverts the logic 0 output 40 so that the output 34 goes high to logic 1. The logic 1 propagates through the delay circuit chain 38 and becomes inverted by the NAND GATE 36 causing a logic 1 output 34. Thus, the output 34 toggles between a logic 1 and a logic 0 state like a free-running oscillator at a frequency determined by the delay time through the delay circuit chain 38 and the NAND GATE 36. Because the closed loop chopper circuit operates as a free-running oscillator, only when clock 14 is logic 1, the circuit functions as a single pulse generator if the clock period is short enough to turn off the NAND GATE 36 before the transition loops back on itself. This circuit has similar disadvantages as the open loop chopper circuit.
In many applications it is desirable for the end of a pulse from a circuit to occur substantially coincident with the generation of a signal from a second circuit. For example, in a memory system it is desirable for the end of a precharge pulse to occur substantially simultaneous with the decoding of the memory address. The memory system will be discussed in more detail infra.
In random access memory (RAM) designs, precharging of a bit line is done to improve the access time of the memory. RAMs are typically configured in rows and columns of memory cells on a single semiconductor chip. A row of memory cells connected to a word line typically comprises a word of memory. An address decoder transmits an enabling signal to a row through a word line. A memory cell in the addressed row of memory cells is either written or read through a corresponding write or read bit line that interconnects each column of memory cells. During a memory read, the read bit line for each column will either have a high or a low voltage for a logic 1 or 0 respectively. Memories are typically designed by compacting memory cells into contiguous areas on the semiconductor chip. In order to maximize memory cell density, the driver circuit for each bit line is designed as small as possible. A sense amplifier (amp) is connected to the end of each bit line in order to amplify its signal and to provide sufficient data output drive current for circuits that receive these signals. A binary bit of information is read out of a memory cell by driving the bit line either to a high or low voltage to represent a logic 1 or logic 0, respectively. Because the signal drive capability of a memory cells is low, the transition time between logic levels is slow. In order to enhance this transition time, the voltage of each bit line is typically set at an intermediate voltage level between high and low voltage levels by a precharger which precharges the bit line so that the voltage on the bit line reaches this intermediate voltage before the address decoding is completed. When the memory cell is read by a signal on the addressed word line, the voltage swing on the precharged bit line is, on the average, about 1/2 the swing of a non-precharged line. Because the voltage swing is less than for a non-precharged line, the transition time is correspondingly reduced.
FIG. 11A shows the timing wave forms of the precharger, the address decoder and the data output when the precharging occurs simultaneously with the address decoding. The read decoder output 42 is a time sequence of decoded read address signals 44 corresponding to a sequence of read addresses 118. A read address 44-1 for one word line is followed by a read address 44-2 to another word line and so forth. For clarity, only two read addresses are shown. While the precharge pulse 46 on a bit line is high, the voltage on the bit line reaches an intermediate voltage level at a time coinciding with the completion of the decoding of the read address 44 and the application of the address signal on the corresponding word line. As shown in FIG. 11A, the end of the precharge pulse 46 coincides with the end of the decoding of address 44-2, or equivalently at the beginning of the address signal on the read decoder output 42. The voltage wave form of the read bit lines 48 is at the intermediate voltage level between high and low levels until a delay time after the end of the precharge pulse. The sense amp 50 detects the voltage level on the bit line and outputs a logic signal as a function of the detected voltage. When the bit line voltage is at the intermediate level, the output of the sense amp is indeterminate. A system which uses this memory cannot use the data on the output of the sense amp until it is determinable. Thus, the system cannot access memory faster than the memory can read the data. During this time, the sense amp output 50 for each bit line is in an unknown state because the read bit lines 48 are at the mid-voltage level. When the read bit lines 48 are no longer being precharged, the read bit lines are driven by the RAM cells and the sense amp forms outputs representing the data read from the read bit lines.
FIG. 11B shows the timing wave forms of the precharger, address decoder and the data output when the precharging occurs earlier than the address decoding completes and the address signal occurs on a word line. The read decoder output 42 functions as discussed above in FIG. 11A. However, FIG. 11B shows the precharge pulse 46 occurring and ending before the end of the decoding of address 44-2. During the precharge pulse, the read bit lines 48 are set to the intermediate voltage level and the sense amp output 50 is in an indeterminate state. After the precharge pulse is turned off, the address decoder is still addressing memory address 44-1 and the read bit lines 48 reestablish voltages corresponding to the data in the memory cells at the old address 44-1 and the sense amp outputs this data. If the system which uses this memory reads the data at this time, the system may not have sufficient time to read the data before the address of the memory cells being read is changed to address 44-2. This change in address causes the read bit lines 48 to change to reflect the data in the memory cells at the next read address 44-2. Thus, the sense amp output 50 has an incorrect output until sometime after the address 44-2 is decoded and the voltage on the bit lines settle to the voltages of the data located in the memory cells of address 44-2.
FIG. 11C shows the timing wave forms of the precharger address decoder and the data output when the precharging occurs after the address decoding completes. The read decoder output 42 functions as discussed above in FIG. 11A. However, FIG. 11C shows the precharged pulse 46 ending after the end of the decoding of the address 44-2. During the precharge pulse 46, the read bit lines 48 are set to the intermediate voltage level and the sense amp output 50 is in an indeterminate state. However, during part of the time that the sense amp output 50 is in an undetermined state, the address decoding of address 44-2 is completed. The memory cells at this address try to output data on each read bit line at the same time that the corresponding precharged pulses on the read bit lines are being held at the intermediate voltage level. At the end of the precharge pulses, the data on the read bit lines reflects the data in the addressed memory cells. Thus, the proper data at the memory address 44-2 to be output on the sense amp output 50 has been delayed.
Ending the precharged pulse before the address is decoded can cause the incorrect value to be output by the sense amp. A precharged pulse that ends after the address is decoded causes a delay in data access. Because most memory systems require faster data access, this is an undesirable condition.
One method for controlling the precharge pulse and the address decoding is to perform these functions consecutively. For example, U.S. Pat. No. 4,558,435 to Hsieh issued Dec. 10, 1985, teaches the sequencing of the precharging and address decoding so that the precharge is completed before initiating the address decoding. An address register transition detector generates a negative going voltage step upon the receipt of a new address. The address transition pulse causes the precharge pulse generator to generate a precharge pulse and simultaneously inhibits the address decoders. A sensing circuit monitors the voltage on the master bit lines and generates a reset pulse when the precharging is completed. This reset pulse disables the precharge pulse generator and simultaneously enables the address decoding. The completion of the address decoding is determined by detecting the return of a read enable pulse that propagates over a dummy line. The dummy line is placed on the silicon and is similar in length and composition to the word lines of the memory in order to simulate the electrical properties of the word line. Thus, the read enable pulse turns on the address decoder, and, as the decoded address propagates along the word line to enable selected memory cells, the read enable pulse also travels along this dummy line so that the read enable pulse returns to set a sense enable signal at the same time that the memory cells are ready to be read. When the sense enable pulse enables the sense amps to read data from the memory cell, the address decoders are disabled, and the system is restored to its initial position prior to the next address change.
The speed of the Hsieh memory system is limited by the cumulative time of the precharging, the address decoding and the reading from the memory cells. In addition, the propagation time through the delay line does not necessarily correspond to the delay through the address decoding circuitry.
Thus it is desirable to provide a pulse generator which produces a pulse substantially coincident with the generation of a signal from a second circuit. This coincident timing should be independent of the temperature, process or power forms of the two circuits. Furthermore, it is desirable that the circuits perform as fast as possible.